1. Field of the Invention
The present invention relates to a semiconductor circuit which generates a high output voltage in a CMOS device having lower channel breakdown voltage.
2. Discussion of Related Art
As a semiconductor device is highly integrated, the channel length of a CMOS transistor forming the semiconductor device becomes small, and thus the channel breakdown voltage is also reduced. Accordingly, higher output voltage cannot be created from the device. To solve this problem, several methods for generating high output voltages in integrated circuits have been proposed. One method is to employ a process for high voltage, and another is to use a shield voltage. The first method requires a special additional process. Thus, the circuit area and its complexity are greater than the method using a shield voltage. Accordingly, the method using the shield voltage is the typical approach to generate a high as voltage in the integrated circuit because it limits the range of voltage applied to each transistor.
This method is described below with reference to FIG. 1. FIG. 1 is a circuit diagram of a conventional semiconductor circuit for generating a high output voltage. Referring to FIG. 1, the semiconductor circuit includes: a first PMOS transistor P1, which receives a shield voltage VSHLD for controlling the operation of the circuit at its gate, and receives an input signal at its source; a second PNOS transistor P2, which receives the signal from the drain of first PMOS transistor P1 at its gate, and receives a predetermined positive voltage VDD at its source; a third PMOS transistor P3, which receives the signal output from the drain of second PMOS transistor P2 at its source, and receives the shield voltage VSHLD at its gate; a first NMOS transistor N1, which receives the shield voltage VSHLD with its gate, and receives the input signal with its drain; a second NMOS transistor N2, which receives at its gate the signal output from the source of first NMOS transistor N1, and its source is grounded; and a third NMOS transistor N3, which is constructed in a manner that its source is connected to the drain of second NMOS transistor N2, its drain receives the voltage applied to the drain of third PMOS transistor P3, and its gate receives shield voltage VSHLD. The substrate bias voltage of first, second and third transistors P1, P2 and P3 are set to positive voltage VDD, and that of first, second and third NMOS transistors are set to the ground voltage.
The above-described semiconductor circuit for preventing the channel breakdown is disclosed in U.S. Pat. No. 5,465,054, and its operation is described below.
When VDD is 10 V, then VSHLD is half of VDD, 5 V. First PMOS transistor P1, third PMOS transistor, first NMOS transistor N1 and third NMOS transistor N3 are controlled by the input voltage VIN. When the input voltage VIN is 10 V (on the source of P1) and the VSHLD voltage is 5 V (on the gate of P1), P1 turns on, so the gate voltage of P2 becomes 10 V. When the gate voltage of P2 is 10 V, i.e., approximately the same as VDD on the source of P2, the second PMOS P2 turns off.
Assuming that the drain of N1 previously was in a LOW voltage state and the gate of N1 is 5 V, N1 turns on and begins to conduct. When the voltage on the source of N1, i.e., the gate voltage of N2, is about 5 V, the second NMOS transistor N2 turns on. Because N2 is turned on, the source of N3 is 0 V and the gate of N3 is 5 V, so N3 turns on causing the drain of N3 to drop to 0 V. The drain of P3 is connected to the drain of N3 and goes to 0 V, so P3 turns off. The PMOS transistors P2 and P3 each have a very big resistivity Roff and VDD voltage is divided in half across P2 and P3. So the source of P3, that is the drain of P2, becomes 5 V, i.e., VDD.div.2.
As described above, regardless of whether the output voltage is changed from 0 V to 10 V, the channel breakdown voltage across the source and drain of second and third PMOS transistors P2 and P3 (which perform a pull-up function), and second and third NMOS transistors N2 and N3 (which perform a pull-down function), remains limited to approximately 5 V. Accordingly, it is possible to create an output voltage that is twice as great as the channel breakdown voltage.
The conventional semiconductor circuit shown in FIG. 1 serves as an inverter. Thus, the semiconductor circuit operates normally if the source potential of first NMOS transistor N1 is in a floating state, when the input signal is "HIGH". Thus, the stability of the entire operation is deteriorated. Furthermore, when driving voltage VDD increases from 10 V to 15 V, in order to create a higher output voltage, the voltage across the source and drain of second and third PMOS transistors P2 and P3, and second and third NMOS transistors N2 and N3 becomes approximately 7.5 V. When driving voltage VDD is increased to 30 V, the voltage across the source and drain of the transistors becomes approximately 15 V.
If the driving positive voltage increases excessively, an excessive voltage is applied across the source and drain of each of transistors P2, P3, N2 and N3, and thus channel breakdown occurs in these transistors, producing poor operation of the circuit. As a result, an output voltage that is twice as great as the channel breakdown voltage cannot be created when the driving voltage is increased above a predetermined limiting value.